Memory RAM Harga – Spesifikasi

Fitur :

JEDEC standard nominal Voltage, 1.35 V operable and 1.5 V endurant
1.5V center-terminated push/pull I/O
Differential bidirectional data strobe
8n-bit prefetch architecture
– Differential clock inputs (CK, CK#)
– 8 internal banks
– Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
– Programmable CAS READ latency (CL)
– Posted CAS additive latency (AL)
– Programmable CAS WRITE latency (CWL) based on tCK
– Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])
– Programmable CAS latency 9, 10 ,11 supported
– Programmable additive latency 0, CL-1, and CL-2 supported
– Programmable CAS Write latency (CWL) = 9, 10, 11
– Selectable BC4 or BL8 on-the-fly (OTF)
– Self refresh mode
– Average Refresh Cycle (Tcase of 0 °C to 95 °C)
— 64ms, 8192 cycle refresh at 0°C to 85°C
— 32ms, 8192 cycle refresh at 85°C to 95°C
– Self refresh temperature (SRT)
– Write leveling
– Multipurpose register
– Output driver calibration
– JEDEC standard 78ball FBGA(x4/x8)
– RoHS compliant